This invention is directed to the art of manufacturing silicon semiconductor devices. Specifically, a process for producing uniform N-channel FETs is provided.
Ion-implantation of JFET structures is capable of very fine geometrical control, i.e., in the fabrication of surface patterns, and thus is of potentially significant value for LSI design and high speed, high reliability performance structures.
However, the ion-implanted N-channel JFET structures of the prior art are necessarily subjected to high temperature processing steps during which gate oxide is grown. These processing steps result in a depletion of the boron dopant at the surface P-type layer of the NJFET, resulting in significantly decreased device performance and overall utility, substantially limiting this valuable implantation process for the formation of NJFET gates. As degradation of the boron implant, particularly by diffusion out of surface silicon into gate oxide, is a necessary consequence of the high temperature processing steps universally followed in the art, strong NJFET surface gate doping through ion implantation has been difficult, if not impossible to secure through prior methods. N-channel IGFETs are also effected by the same boron surface depletion problem.
Generally, the boron depletion phenomenon overcome by the instant invention is believed to occur due to a natural unavoidable characteristic of dopants in general, and boron dopant in particular. Generally, boron or other p-type dopant is introduced into the substrate through surface implantation and deep diffusion, or similar means, which results in a curve of generally decreasing dopant levels at increasing substrate depth until a desired background dopant level is reached at the region of the lower P-type gate of an NJFET device.
This decreasing curve, as is discussed below, is desirable. However, the characteristics of this curve cannot be preserved upon high temperature processing, as practiced in the industry. It is the natural tendency of boron, and many other dopants, to migrate into surface oxide under the influence of high temperature. At the surface regions of the NJFET substrate, where the highest P-type dopant concentration is desired, this migration tends to result in loss of boron from the surface of the substrate (P-type well), decreasing the concentration in the surface region. The depletion is not only down into the substrate, but up into the protective layer. In most processing for a silicon substrate, the protective layers are silicon oxides. Since boron has a solid soluability in silicon oxide greater than in silicon, the depletion is accelerated at the silicon-silicon oxide interface. As a result, the end product has a P-type dopant concentration curve with a depletion area at the surface region of the substrate. Additionally, as the amount of depletion will be controlled and effected by various parameters including the severity of temperature and length of time of processing, the loss of boron is variable throughout a series of produced structures. This variability is especially critical when the N-channel is to be formed by ion-implantation, e.g., using phosphorous. The solid solubility of phosphorous is, contrary to boron, greater in silicon than the surface oxide, thus resulting in enhancement of phosphorous concentration in the same surface layer depleted of boron. This can severely affect FET performance, particularly prevention of surface inversion and drain-source surface (punch-through) breakdown.
Accordingly, it is one object of this invention to provide a method for construction of uniform NFET through ion-implantation.
It is another object of the invention to provide a method for producing a high quality NFET suitable for use in advanced technologies, such as monolithic design circuits.
These and other objects of the invention are attained by performing a unique boron compensation implant after all high temperature processing has been completed. For JFET and IGFET, the background gate or body regions respectively are heavily doped to the final desired level, and thereafter all bipolar or other processing, including all high-temperature processing is completed. After high-temperature processing steps have been completed, a first protective layer is formed on the silicon wafer surface, and boron dopant is implanted in the silicon surface to compensate for the boron depletion. This implant is performed to have a concentration peak in the first protective layer. Thereafter, the first layer is stripped and a second protective layer is formed and phosphorous is then implanted to from the N-channel, thereby completing the NJFET structure. For IGFETs, the compensation may be performed before or after the source-drain formation.